CS5346-CQZR【PDF 12/38 页】IC ADC AUD 103DB 200KHZ 48-LQFP

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Sheet目录1991

8页 9页 10页 11页 [12页]13页 14页 15页 16页

DS861PP3

CS5346

TABLE OF CONTENTS

1. PIN DESCRIPTIONS - CS5346 ............................................................................................................. 5

2. PIN COMPATIBILITY - CS5345/CS5346 DIFFERENCES ..................................................................... 7

3. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 8

RECOMMENDED OPERATING CONDITIONS ................................................................................... 8

ABSOLUTE MAXIMUM RATINGS .......................................................................................................8

ANALOG CHARACTERISTICS ............................................................................................................ 9

ANALOG CHARACTERISTICS CONT. .............................................................................................. 10

DIGITAL FILTER CHARACTERISTICS .............................................................................................. 11

DC ELECTRICAL CHARACTERISTICS ............................................................................................. 12

DIGITAL INTERFACE CHARACTERISTICS ...................................................................................... 13

SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT ............................................................. 14

SWITCHING CHARACTERISTICS - CONTROL PORT - IC FORMAT ............................................ 16

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT ........................................... 17

4. TYPICAL CONNECTION DIAGRAM ................................................................................................... 18

5. APPLICATIONS ................................................................................................................................... 19

5.1 Recommended Power-Up Sequence ............................................................................................. 19

5.2 System Clocking ............................................................................................................................. 19

5.2.1 Master Clock ......................................................................................................................... 19

5.2.2 Master Mode ......................................................................................................................... 20

5.2.3 Slave Mode ........................................................................................................................... 20

5.3 High-Pass Filter and DC Offset Calibration .................................................................................... 20

5.4 Analog Input Multiplexer, PGA, and Mic Gain ................................................................................21

5.5 Input Connections ........................................................................................................................... 21

5.5.1 Analog Input Configuration for 1 VRMS Input Levels ............................................................ 21

5.5.2 Analog Input Configuration for 2 VRMS Input Levels ............................................................ 22

5.6 PGA Auxiliary Analog Output ......................................................................................................... 23

5.7 Control Port Description and Timing ............................................................................................... 23

5.7.1 SPI Mode ............................................................................................................................... 23

5.7.2 IC Mode ................................................................................................................................ 24

5.8 Interrupts and Overflow .................................................................................................................. 25

5.9 Reset .............................................................................................................................................. 26

5.10 Synchronization of Multiple Devices ............................................................................................. 26

5.11 Grounding and Power Supply Decoupling .................................................................................... 26

6. REGISTER QUICK REFERENCE ........................................................................................................ 27

7. REGISTER DESCRIPTION .................................................................................................................. 28

7.1 Chip ID - Register 01h .................................................................................................................... 28

7.2 Power Control - Address 02h ......................................................................................................... 28

7.2.1 Freeze (Bit 7) ......................................................................................................................... 28

7.2.2 Power-Down MIC (Bit 3) ........................................................................................................ 28

7.2.3 Power-Down ADC (Bit 2) ....................................................................................................... 28

7.2.4 Power-Down Device (Bit 0) ................................................................................................... 28

7.3 ADC Control - Address 04h ............................................................................................................ 29

7.3.1 Functional Mode (Bits 7:6) .................................................................................................... 29

7.3.2 Digital Interface Format (Bit 4) .............................................................................................. 29

7.3.3 Mute (Bit 2) ............................................................................................................................ 29

7.3.4 High-Pass Filter Freeze (Bit 1) .............................................................................................. 29

7.3.5 Master / Slave Mode (Bit 0) ................................................................................................... 29

7.4 MCLK Frequency - Address 05h .................................................................................................... 30

7.4.1 Master Clock Dividers (Bits 6:4) ............................................................................................ 30

7.5 PGAOut Control - Address 06h ...................................................................................................... 30

7.5.1 PGAOut Source Select (Bit 6) ............................................................................................... 30

7.6 Channel B PGA Control - Address 07h .......................................................................................... 30

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